1. Field of the Invention
The present invention is generally in the field of electronic circuits and systems. More specifically, the present invention is in the field of control circuits and systems.
2. Background Art
Memory controllers form an integral part of many computer systems. For instance, memory controllers may manage the flow of data to external memory devices. Memory controllers may also periodically refresh dynamic memory devices to prevent data loss. To ensure suitability for consumer use, memory controllers, including the chip on which they reside, are often subject to rigorous tests with automated test equipment (ATE). Typically, ATE supplies a chip containing a memory controller with a test vector and determines whether the chip responds according to design specifications.
However, it is often difficult to test a chip containing a conventional memory controller at the full rate that the conventional memory controller transfers data to a memory device (i.e., “at-speed”). As a result, conventional approaches to testing memory controllers typically do so at reduced speeds. Though potentially useful, reduced speed testing does not optimize test times and may inaccurately represent the functionality of a chip containing a memory controller at-speed. Moreover, conventional memory controllers have typically required auxiliary tests to accommodate manufacturing variations and the non-deterministic behavior of internal interfaces. Unfortunately, these auxiliary tests often increase test times.
Accordingly, there is a need to overcome the drawbacks and deficiencies in the art by providing a memory controller that facilitates efficient at-speed testing with a single set of functional test vectors.